Skew and Delay Optimization for Reliable Buffered Clock Trees

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S. Pullela, N. Menezes and L.T. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.

An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules

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S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.