Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization
S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.
Archive for month: June, 1993
Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpD.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.
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