Finite-Pole Macromodels of Transmission Lines for Circuit Simulation

S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.

AWE-Inspired

V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, “Proceedings Custom Integrated Circuits Conference”, (Invited Tutorial Paper), May 1993.

Skew Reduction in Clock Trees Using Wire Width Optimization

N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.