## NOTE: The list of papers on this web page was created to help

to understand background of the yield related research conducted by W. Maly and his students. However, it, by no means, should be seen as an adequate list of yield modeling related papers.incoming graduate students

## Introduction

The papers listed in this selection are focused on yield modeling and analysis in application for Design for Manufacturability. The papers listed in boldface have introduced key ideas which then has been developed in the subsequent papers. They are arranged in the following ten groups:

1. Yield Models - describing functional yield models in terms of IC design attributes and process defect characteristics.

2. Defect Size/Density Extraction - proposing methodologies to characterize manufacturing processes.

3. Critical Area Extraction - suggesting efficient algorithms needed for extraction IC design yield relevant attributes.

4. Yield Analysis - discussing methods for detecting which design attributes are really yield relevant.

5. Defect Modeling - analyzing contamination-defect-fault relationship

6. Yield Loss with Circuit Redundancy - stressing the need per-node yield prediction.

7. Yield-Oriented Layout Optimization - channel routing for yield and testability

8. Yield Learning - introducing methodology for the time domain forecasting of yield changes due to process modifications and contamination control.

9. Parametric Yield Loss - discussing non defect related yield loss.

10. Tutorials - providing overviews of CAD oriented yield-related arena.

## 1. Yield Models

[m1] W. Maly and J. Deszczka, "Yield Estimation Model for VLSI Artwork Evaluation," Electronics Letters, 17th March 1983, Vol. 19, No. 6, pp. 226-227.

[m2] W. Maly, "Modeling of Point Defect Related Yield Losses for CAD of VLSI Circuits," Proc. of ICCAD-84, 1984, pp. 161-163.[m3] W. Maly, "Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits," IEEE Trans. on CAD, July 1985, pp. 161-177.

[m4] W. Maly, H.T. Heineken and F. Agricola, "A Simple New Yield Model," Semiconductor International, July 94, pp. 148-154.

[m5] H.T. Heineken, J. Khare and W. Maly, "Yield Loss Forecasting in the Early Phases of the VLSI Design Process," Proc. CICC -96 pp. 27-30.

[m6] H. T. Heineken and W. Maly, "Interconnect Yield Model for Manufacturability Prediction in Synthesis of Standard Cell Based Designs," Proceedings of ICCAD-96 pp. 368-373.[m7] W. A. Pleskacz and W. Maly "Improved Yield Model for Submicron Domain," In Proceedings of Defect and Fault Tolerance in VLSI Systems, Paris, Oct. 1997 pp. 2-10.

Comment: Paper [m1] introduces the concept of critical area and proposes an extension to the Poisson yield model (such that interaction between varying defect size and layout geometry can be accounted for). Both concepts are than published again and discussed by others in many papers (usually without reference to [m1] -- perhaps partially due to the unusual place of publication). Papers [m2] and [m3] expand the critical area concept and propose a methodology for critical area computation (using "virtual layout concept ), as well as application of the critical area-based yield model for design rule optimization and feature size scaling. The most common references related to the critical area concept are either: A.V. Ferris-Prabhu, "Modeling of Critical Area in Yield Forecasts", Journal of Solid-State Circuits, SC-20(4), pp. 878-880, 1985. [15] or A.V. Ferris-Prabhu, "Role of Defect Size Distributions in Yield Modeling," IEEE Trans. on Electron Devices, vol. ED-32, no. 9, pp. 1727-1736, September 1985. Also very frequently the paper: C. H. Stapper, "Modeling of Integrated Circuit Defect Sensitivities", IBM Journal of Research and Development, 27(6), pp. 549-557, November 1983 is credited with the introduction of the critical area concept. Even if these papers have not been first they should be studied carefully and referenced. The paper [m4] proposes a new yield model using instead of the critical area the density of design (as a measure of defect sensitivity). The paper [m5] also approximates defect sensitivity with simplified measures of critical area. The paper [m6] estimates interconnect yield by estimating interconnect critical areas from the gate-level netlist. The paper [m7] a yield model which takes into account lithography induced deformations as illustrated in [ce3] later.

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## 2. Defect Size Extraction

[de1] W. Maly, M.E. Thomas, J.D. Chinn and D.M. Campbell, "Double-Bridge Test Structure for the Evaluation of Type Size and Density of Spot Defects," in Designing for Yield Workshop, Oxford, England 1987.[de2] J.A. Doi, M.E. Thomas and W. Maly, "Detection and Physical Characterizations of Spot Defects in Metal IC Interconnections," 172nd Meeting of the Electrochemical Society, Honolulu 1987, p. 637.

[de3] W. Maly, M.E. Thomas, J.D. Chinn and D.M. Campbell, "Measurements of Type, Size and Density of Spot Defects," in "Design for Yield" edited by W.R. Moore, W. Maly and A.J. Strojwas, published by Adam Hilger, Bristol and Boston, 1988.

[de4] J. Khare, B.J. Daniels, D.M. Campbell, M.E. Thomas and W. Maly, "Extraction of Defect Characteristic for Yield Estimation Using the Double Bridge Test Structure," 1991 International Symposium on VLSI Technology, Systems, and Applications, May 22-24, 1991, Taipei, Taiwan, pp. 428 - 432.

[de5] J. Khare, S. Griep, W. Maly, and D. Schmitt-Landsiedel, "SRAM-based Extraction of Defect Characteristics," Proceedings of the International Conference on Microelectronic Test Structures, San Diego, March 1994, pp. 98-107.

[de6] J. Khare, W. Maly and M. E, Thomas, "Extraction of Defect Size Distributions in an IC Layer Using Test Structure Data," IEEE Transactions of Semiconductor Manufacturing, pp. 354-368, vol. 7. no. 3, Aug. 1994.

[de7] J. Khare, W. Maly, S. Griep and D. Schmitt-Landsiedel, "Yield-Oriented Computer-Aided Defect Diagnosis," IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No.2, May 1995, pp. 195-205.

Comment: The critical area-based yield models cannot be used unless defect size distribution is known. Papers [de1] through [de7] discuss this problem in detail. There are very few papers other than the papers listed above which discuss the extraction of the defect size distributions.

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## 3. Critical Area Extraction

[ce1] P. K. Nag and W. Maly, "Yield Estimation of VLSI Circuits," Techcon90, Oct. 16-18, 1990. San Jose.

[ce2] P.K. Nag and W. Maly, "Hierarchical Extraction of Critical Area for Shorts in Very Large ICs," in Proceedings of The IEEE International Workshop on Detect and Fault Tolerance in VLSI Systems, IEEE Computer Society Press 1995, pp. 10-18.

[ce3] I. Bubel, W. Maly, T. Waas, P.K. Nag, H. Hartmann, D. Schmitt-Landsiedel and S. Griep, "AFFCCA: A Tool for Critical Area Analysis with Circular Defects and Lithography Deformed Layout," in Proceedings of The IEEE International Workshop on Detect and Fault Tolerance in VLSI Systems, IEEE Computer Society Press 1995, pp. 19-27.

[ce4] C. Ouyang and W. Maly, "Efficient Extraction of Critical Area in Large VLSI ICs," Proc. IEEE International Workshop on Defect and Fault Tolerance of VLSI Systems, 1996 pp. 301-304.

[ce5] C. Ouyang, W. Pleskacz, and W. Maly, "Extraction of Critical Area for Opens in Large VLSI Circuits," Proc. IEEE International Workshop on Defect and Fault Tolerance of VLSI Systems, 1996 pp. 21-29.

Comment: The extraction of the critical area from IC design database have been discussed in many papers. Usually, however, these papers have been focused on a particular detail of applied algorithms and on rather small circuits. The key problems addressed by the above listed papers are complexity of computations of the critical area ([ce1] and [ce2]) and the impact of the process induced layout deformation on the critical area extraction [ce3]. The papers [ce4] and [ce5] describe the critical area extraction methodology for shorts and opens in very large ICs.

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## 4. Yield Analysis

[ya1] W. Maly, B. Trifilo, R.A. Hughes, and A. Miller, "Yield Diagnosis Through Interpretation of Tester Data," Proc. of ITC-87, Washington D.C., 1987.

[ya2] H.T. Heineken and W. Maly, "Manufacturability Analysis Environment - MAPEX," Proceedings of the 1994 Custom Integrated Circuits Conference , pp. 309-312, May 1994.[ya3] D. Schmitt-Landsiedel, D. Keitel-Schulz, J. Khare, S. Griep and W. Maly, "Critical Area Analysis for Design Based Yield Improvements of VLSI Circuits," Quality and Reliability Engineering International, Vol. 11, pp. 225-232, 1995.

[ya4] W. Maly, C. Ouyang, S. Ghosh, and S. Maturi, "Detection of Antennae Effect in VLSI Designs," Proc. of the Int. Symposium on defect and Fault Tolerance in VLSI Systems, 1996, pp. 86-94.[ya5] R. K. Nurani, A. J. Strojwas, W. Maly, C. Ouyang, W. Shindo, R. Akella, M. McIntyre, and J. Derrett, " In-Line Yield Prediction Methodologies Using Patterned Wafer Inspection Information," Int. Symposium on Semiconductor Manufacturing, pp. 243-248, Sept. 1996.

Comment: Yield analysis is a process that reveals relationships between design and fabrication attributes, and yield loss. The above three papers illustrate one of the many possible approaches. The paper [ya2] proposes a simple, common sense but effective framework for yield analysis. The paper [ya4] describes a method of extracting the statistics of a layout related to the antenna effect using capabilities available in commercial verification tool. The paper [ya5] describes successful industrial application of the critical area based yield prediction.

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## 5. Defect Modeling

[dm1] W. Maly, F.J. Ferguson and J.P. Shen, "Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells," Proc. International Test Conference, pp. 390-399, 1984.[dm2] J. P. Shen, W. Maly, and F. J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," Special Issue of IEEE Design&Test of Computers, pp. 11-26, December 1985.

[dm3] J. Khare and W. Maly, "Inductive Contamination Analysis (ICA) with SRAM Application," IEEE International Test Conference, pp. 552-560, October 1995.[dm4] J. Khare and W. Maly, "From Contamination to Detect Fault and Yield Loss," Kluwer Academic Publishers, April 1996.

[dm5] J. Khare, W. Maly, and N. Tiday, "Fault Characterization of Standard Cell Libraries Using Inductive Contamination Analysis (ICA),"Proceedings of the 1996 VLSI Test Symposium, April 1996.

[dm6] J. Khare and W. Maly, "Rapid Failure Analysis Using Contamination-Defect-Fault (CDF) Simulator," IEEE Trans. on Semiconductor Manufacturing, vol. 9, no. 4, Nov. 1996, pp. 512-526.

Comment: Papers listed in this group attempt to build a bridge between the "observable" parameters of manufacturing contaminations and resulting circuit malfunctions. This important problem has been discussed in a relatively large number of papers published as a follow-up of [dm1]. The most comprehensive and widely referred papers following methodology proposed in [dm1] are: H. Walker and S.W. Director, "VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD 5(4), pp. 541-556, 1986, Alvin Jee and F. Joel Ferguson, "Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits," Proceedings of the 1993 IEEE VLSI Test Symposium, 1993, and J. Pineda de Gyvez and C. Di, "IC Defect Sensitivity for Footprint-Type Spot Defects" IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 11, No. 5, pp. 638-658. The book [dm4] is the latest publication in this area which describes simulator CODEF - the most complete and perhaps the most accurate attempt in contamination-defect-fault simulation.

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## 6. Yield Loss with Circuit Redundancy

[yr1] W. Maly, "Design Methodology for Defect Tolerant Integrated Circuits," Proc. of CICC-88, Rochester, NY, May 1988.[yr2] J. Khare, D. Feltham, and W. Maly, " Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits," IEEE Journal of Solid State Circuits, No. 2, pp. 146-156, Feb. 1993.

[yr3] D. Gaitonde, D.M.H. Walker, and W. Maly, "Accurate Yield Estimation of Circuits with Redundant Elements", in Proceedings of The IEEE International Workshop on Detect and Fault Tolerance in VLSI Systems, pp. 155-163, 1995.

Comment: Yield models for circuits with redundant components have been published in large numbers. The papers included in this selection stress the need to base such yield modeling on critical area extraction performed on a per node basis. The paper [yr1] also introduces the concept of local (which are repairable) and global nodes (which are not). This concept was used in [yr2] and [yr3] to assess the cost effectiveness of redundancy applications in non memory architectures.

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## 7. Yield-Oriented Layout Optimization

[yo1] D. Feltham, J. Khare, and W. Maly, "Design for Testability View on Placement and Routing," Proc. EuroDAC 92, Hamburg, Germany, pp. 382-387, Aug. 1992.[yo21] J. Khare, S. Mitra, P. K. Nag, W. Maly and R. Rutenbar, "Testability-Oriented Channel Routing," Proc. 8th Annual VLSI Design Symposium, N. Delhi, India, pp. 208-213, Jan 1995.

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## 8. Yield Learning

[yl1] P. Nag and W. Maly," Y4 - A Yield Learning Simulator," Eight Annual SRC/ARPA CIM-IC Workshop, Aug. 1993.

[yl2] P.K. Nag and W. Maly, "Yield Learning Simulation," Proc. of TECHCON-93, Atlanta, pp. 280-282, Oct. 1993.

[yl3] P. K. Nag, W. Maly, and H. Jacobs, "Simulation of Yield/Cost Learning Curves Using Y4," Trans. on Semiconductor Manufacturing, vol. 10, no. 2, pp. 256-266, May 1997

[yl4] P.K. Nag, W. Maly, and H. Jacobs, "Forecasting Cost Yield," submitted to Semiconductor International, Jan 1998.

Comment: Yield is not a static figure - it changes due to inherent fluctuations in process conditions and process corrective activities. Consequently there is a need for yield forecasts which can estimate yield as a function of time. [yl1] proposes simulation technique which can fulfill such goal. Subsequent publications describe various aspects of implementation of yield forecaster Y4. [yl3] gives a more detailed description of modeling considerations and provides more complex examples of yield and cost learning impact. [yl4] provides latest results of simulations using Y4.

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## 9. Parametric Yield Loss

[yp1] W. Maly and T. Gutt, "Base and Emitter Simulation Model", Proc. of International Conference on Computer Aided Design and Manufacturing of Electronic Components, Circuits and Systems, pp. 38-42, 1979.

[yp2] W. Maly and A.J. Strojwas, "Simulation of Bipolar Elements for Statistical Circuit Design," Proc. of IEEE International Symposium on Circuits and Systems, pp. 788-791, 1979.

[yp3] W. Maly, A. J. Strojwas and S. W. Director, "Fabrication Based Statistical Design of Monolithic IC's," Proc. of IEEE International Symposium on Circuits and Systems, pp. 135-138, 1981.[yp4] W. Maly and A. J. Strojwas, "Statistical Simulation of the IC Manufacturing Process", IEEE Trans. on CAD of IC and Systems, Vol. CAD-1, No. 3, pp. 120-131, July 1982.

Comment: Yield loss modeling arena also covers yield loss mechanisms which are not defect-based. The literature covering these mechanism is also very rich. The above papers are included in this listing to illustrate some of the early attempts which have enabled process-based simulation of parametric yield loss.

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## 10. Tutorials

[t1] W. Maly, A. J. Strojwas, and S. W. Director, "Yield Prediction and Estimation: A Unified Framework," IEEE Trans. on Computer Aided Design, January 1986.

[t2] W. Maly, "Realistic Fault Modeling for VLSI Testing Tutorial ," Proc. of 24th DA Conference, June 1987.[t3] W. Maly, W. R. Moore and A. J. Strojwas, "Yield Loss Mechanisms and Defect Tolerance," in "Design for Yield" edited by W.R. Moore, W. Maly, and A.J. Strojwas, published by Adam Hilger, Bristol and Boston, 1988.

[t4] W. Maly, "Yield Models - Comparative Study," in Defect and Fault Tolerance in VLSI Systems, Ed. by C. Stapper at. al., Plenum Press, New York, 1990.

[t5] W. Maly, Invited "Computer-Aided Design for VLSI Circuit Manufacturability," Proc. of IEEE, Vol. 78, No. 2, pp. 356-390, Feb. 1990.

[t6] W. Maly, Invited, "Cost of Silicon Viewed from VLSI Design Perspective," Proc. of DAC-94, San Diego, pp. 135-142, June 1994.

[t7] S.W. Director and W. Maly, Editors, "Advances in CAD for VLSI Volume 8: Statistical Approaches to VLSI Design," North Holland, 1994.

[t8] W. Maly, H. T. Heineken, J. Khare, and P. K. Nag, "Design for Manufacturability in Submicron Domain," Proc. ICCAD 96 pp. 690-697.

[t9] W. Maly, "The future of IC Design, Testing and Manufacturing," IEEE Design and Test of Computers, vol. 13, no. 4. pp. 8, 88-91.

[t10] W. Maly, H. T. Heineken, J. Khare, and P. K. Nag, "Design-Manufacturing Interface: Part I - Vision," Design Automation and Test in Europe, Feb 1998, pp.550-556 .

[t11] W. Maly, H. T. Heineken, J. Khare, P. K. Nag and P. Simon, "Design-Manufacturing Interface: Part II - Applications," Design Automation and Test in Europe, Feb 1998, pp. 556-562.

[t12] W. Maly, "Testing-Based Failure Analysis: A Critical Component of the SIA Roadmap Vision," in Proc. of the 23rd Int. Symposium for Testing and Failure Analysis, pp. 3-6, Oct. 1997.

Comment: There is a lot of the overlap in the above listed tutorials [t4], [t5], and [t6] are covering the entire area to the extent needed in CAD-based yield modeling arena. In last couple of years further progress has been made, which is covered in [t8].