Dr. Maly's research interests have been focused on the interfaces between VLSI design, testing and manufacturing with the stress on the stochastic nature of phenomena relating these three VLSI domains. He has authored, co-authored and edited a number of books, journal and conferences papers, as well as patents, which have attempted to promote integration of design, test and manufacturing. Among his publications addressing the above field are papers introducing: statistical process simulation, layout-oriented yield modeling, defect-based approaches to fault modeling (including inductive fault analysis) as well as new design for manufacturability CAD strategies and defect/quality oriented testing methodologies.
Dr. Maly was elected an IEEE Fellow in 1990 and has been recipient or co-recipient of various awards including honors for his Ph.D. thesis, Ministry of Higher Education of Poland Research Award, Carnegie Mellon's Benjamin Richard Teare Teaching Award, AT&T Foundation Award for Excellence in Instructing of Engineering Students, Fellowship from Deutsche Forschungsgemeinschaft, SRC 1992 Technical Excellence Award, Best Paper Award from the International Test Conference 1990, the Best Paper Award from ESREF 94 , the 1994 Best Paper Award from IEEE Transaction on Semiconductor Manufacturing, 1995 Best Paper Award from 1996 European Design and Test Conference and Eta Kappa Nu CMU Sigma Chapter Excellence in Teaching Award.