Wojciech P. Maly

Name:

Wojciech P. Maly
maly@ece.cmu.edu
Whitaker Professor
Electrical and Computer Engineering
Bio [pdf] and Short Personal Web Page

Mailing Address:

Hamerschlag Hall 2126
Electrical and Computer Engineering
Carnegie Mellon University
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA

Phones:
(Voice) 412-268-6637
(FAX) 412-268-3204
Secretary:

Judy Bandola
Hamerschlag Hall 2107
412-268-2224 (judy@ece.cmu.edu)

Students and Associates:

Research Interests:

Analysis and modeling of the IC industry trends
VLSI design
Design for manufacturability (DFM) of VLSI circuits
Design for testability (DFT)
Understanding and modeling of IC failures
Defect oriented testing
Yield modeling
(Examples of current projects)

Current Teaching

18-322: Analysis and Design of Digital Integrated Circuits
18-525: Integrated Circuit Design Project

Selected Books

  1. W. Maly, "Atlas of IC Technologies - An Introduction to VLSI Processes", The Benjamin/Cummings Publishing Company, Inc., 1987.
  2. S.W. Director and W. Maly, Editors, "Advances in CAD for VLSI Volume 8: Statistical Approaches to VLSI Design", North Holland, 1994.
  3. J. Khare and W. Maly, “From Contamination to Detect Fault and Yield Loss,” Kluwer Academic Publisher, 1996.
Sample of Papers
 
  1. W. Maly, "Computer-Aided Design for VLSI Circuit Manufacturability," Proc. of IEEE, Vol. 78, No. 2, Feb. 1990.
  2. W. Maly, "Prospects for WSI: A Manufacturing Perspective," IEEE Computer, Feb. 1992.
  3. J. Khare, D. Feltham and W. Maly, " Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits," IEEE Journal of Solid State Circuits, Feb. 1993, No. 2.
  4. W. Maly, "Cost of Silicon Viewed from VLSI Design Perspective", Proc. of DAC-94, San Diego, June 1994. [pdf]
  5. J. Khare, W. Maly, S. Griep and D. Schmitt-Landsiedel, "Yield-Oriented Computer-Aided Defect Diagnosis," IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No.2, May 1995.
  6. T. E. Marchok, A. El-Maleh, J. Rajski, and W. Maly, "Testability Implications of Performance Driven Logic Synthesis", IEEE Design & Test of Computers, Vol. 12, No. 2, June 1995.
  7. A. Gattiker and W. Maly, "Current Signatures ", 1996 IEEE VLSI Test Symposium, April 1996.
  8. P.K. Nag, W. Maly and H. Jacobs, “Simulation of Yield/Cost Learning Curves with Y4,” IEEE Transactions on Semiconductor Manufacturing, May 1997, Vol. 10, No. 2, pp. 256-266.
  9. W. Maly, "The Future of IC Design, Testing and Manufacturing," IEEE Design & Test of Computers, Vol. 13, No. 4, pp. 8, 88-91. [pdf]
 
Sample of Talks
 
  1. W. Maly, "New and Not-So-New TEST CHALLENGES for the Next Decade," International Test Conference, Washington D.C., October 1996. [pdf]
  2. W. Maly, "SIA Road Map and DESIGN&TEST," UC Berkeley, April 1997. [pdf]