Improving DRAM Performance by Parallelizing Refreshes with Accesses
HAT: Heterogeneous Adaptive Throttling for On-Chip Networks.
Staged Memory Scheduling: Achieving High Performance
and Scalability in Heterogeneous Systems.
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect.
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism.
HiRD: A Low-Complexity, Energy-Efficient Hierarchical Ring Interconnect.