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This project proposes and investigates GraphGen, a domain-specific compiler that accepts graph algorithms described in a widely used vertex-centric graph specification to target a diverse range of non-Von-Neumann accelerator platforms. The goal of GraphGen is to enable application- and algorithm-level programmers without specific platform expertise to nevertheless be able to take advantage of the performance and energy efficiency of accelerator platforms. The GraphGen compilation approach produces an executable for a standard Graph Execution Model (GEM). Akin to an ISA for graph computations, GEM is a fixed low-level abstraction designed to capture arbitrary graph computations in general and to permit efficient direct support in hardware or light-weight interpretation in software. Once a platform specialist has created GEM support, the platform can be used to execute arbitrary graph computations compiled by GraphGen from a vertex-centric graph specification input. Conversely, the same specification input can be retargeted to any GEM-enabled platform. Aside from being able to run graph algorithms on existing accelerator platforms (FPGAs, GPUs), there is also opportunity to investigate novel dedicated graph processor architectures. This is a project in collaboration with Dr. Eriko Nurvitadhi of Intel ISTC. Funding for this work has been provided, in part, by the National Science Foundation (CCF-1320725) and Intel ISTC.
- Marie Nguyen
- Yu Wang
- GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martinez, Carlos Guestrin. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2014.
- GraphGen for CoRAM: Graph Computation on FPGAs. Third Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL), December 2013.
- GraphGen: Design Compiler for Graph Computation. Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-4), February 2013.
- Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (co-organized with Derek Chiou and Joel Emer)