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—fpga_prototyping_and_emulation_of_computer_systems [2017/09/29 14:11] – external edit 127.0.0.1
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 +====== FPGA Prototyping and Emulation of Computer Systems ======
  
 +This research explores the application of Field Programmable Gate Arrays (FPGA) and High-level Hardware Synthesis technologies in computer systems prototyping and emulation.  This research has been supported in funding and/or equipment by NSF, FCRP/C2S2, SUN, and Xilinx.  Please see the [[http://www.ece.cmu.edu/~protoflex/ | ProtoFlex]] project page for complete and up-to-date details.  We have made the [[http://www.ece.cmu.edu/~protoflex/ | ProtoFlex FPGA-accelerated simulator]] opensource.  Please also visit the related [[http://parsa.epfl.ch/simflex | SimFlex]] project on multiprocessor simulation (in software) and the multi-university [[http://ramp.eecs.berkeley.edu/|RAMP]] project. 
 +
 +  * **Students**
 +    * [[http://www.ece.cmu.edu/~echung |Eric Chung]]
 +    * [[http://www.cs.cmu.edu/~mpapamic/home/ |Michael Papamichael]]
 +    * [[http://www.ece.cmu.edu/~enurvita |Eriko Nurvitadhi]]  
 +  * **ProtoFlex Opensource** ([[http://www.ece.cmu.edu/~protoflex/ |website]])
 +  * **[[http://transplant.sunsource.net/ |OpenSPARC T1: Architectural Transplant]]** (Transplants state from architectural simulators into the OpenSPARC RTL for continued execution)
 +  * **Publications**
 +    * **FPGA-Accelerated Simulation of Computer Systems**. H. Angepat, D. Chiou, E. S. Chung, and  J. C. Hoe. Synthesis Lectures on Computer Architecture #29, Morgan &Claypool, 2014. ([[http://www.morganclaypool.com/doi/abs/10.2200/S00586ED1V01Y201407CAC029 |pdf]])
 +    * **Fast Scalable FPGA-Based Network-on-Chip Simulation Models**. M. K. Papamichael. Formal Methods and Models for Codesign (MEMOCODE), July 2011. ([[http://www.ece.cmu.edu/~jhoe/distribution/2011/mc11.pdf |pdf]])
 +    * **FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations**. M.Papamichael, J. C. Hoe and O. Mutlu. International Symposium on Networks-on-Chip (NOCS), May 2011. ([[http://www.ece.cmu.edu/~jhoe/distribution/2011/nocs11.pdf |pdf]])
 +    * **High-level Design and Validation of the BlueSPARC Multithreaded Processor**. E. S. Chung and J. C. Hoe. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Issue 10, pp 1459-1470, October 2010.  ([[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5580230|ieee]]) //(This is the full journal version of the MEMOCODE 2009 paper.)//
 +    * **Implementing a High-performance Multithreaded Microprocessor: A Case Study in High-level Design and Validation**. E. S. Chung, J. C. Hoe. Formal Methods and Models for Codesign (MEMOCODE), July 2009. ([[http://www.ece.cmu.edu/~jhoe/distribution/2009/mc09.pdf |pdf]])
 +    * **ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs**. E. S. Chung, M. K. Papamichael, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 2, June 2009. ([[http://portal.acm.org/citation.cfm?id=1534916.1534925 |acm]]) //(This is the full journal version of the FPGA 2008 paper.)//
 +    * **A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs**. E. S. Chung, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. International Symposium on Field Programmable Gate Arrays (FPGA), February 2008. ([[http://www.ece.cmu.edu/~jhoe/distribution/2008/fpga08.pdf |pdf]])
 +    * **RAMP: A Research Accelerator for Multiple Processors**. J. Wawrzynek, D. A. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, K. Asanovic. IEEE Micro, Volume 27, Number 2 , March/April 2007. ([[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4287395 |ieee]])
 +    * **RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform**. Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, S.-L. Lu, M. Oskin, D. Patterson, J. Rabaey, J. Wawrzynek. September 2005. ([[http://www.ece.cmu.edu/~jhoe/distribution/2005/ramp-nsf2005.pdf |pdf]]) //(note: this is the tech report version of the original 2005 NSF proposal on RAMP.)//
 +    * **In-System FPGA Prototyping of an Itanium Microarchitecture**. R. Wunderlich and J. C. Hoe.  International Conference on Computer Design (ICCD), October 2004. ([[http://www.ece.cmu.edu/~jhoe/distribution/2004/iccd04.pdf |pdf]])
 +    * **High-Level Modeling and FPGA Prototyping of Microprocessors**. J. Ray and J. C. Hoe. International Symposium on Field Programmable Gate Arrays (FPGA), February 2003.  ([[http://www.ece.cmu.edu/~jhoe/distribution/2003/fpga03.pdf |pdf]])