This is an old revision of the document!
Despite their promise in both processing performance and efficiency, today’s FPGAs are woefully inadequate as computing devices, particularly due to their lack of a standard native memory architecture. In a major departure from conventional FPGAs (which are designed to compete with ASIC technologies) the CoRAM (Connected RAM) project endeavors to completely rethink the FPGA architecture from scratch to create a new generation of first-class reconfigurable computing devices. The goal of the CoRAM project is to harness the full potential of FPGAs for computing by introducing a proper memory architecture that serves as a portable, high-performance bridge between the distributed in-fabric computation kernels and the external off-chip memory. In support of this architecture, the CoRAM project will also study and develop the associated mechanisms, from the microarchitecture-level down to the circuit-level, using a combination of FPGA-based prototypes and test chips. This is a joint project with Prof. Ken Mai. Funding for this work is provided, in part, by the National Science Foundation (CCF-1012851) and by Altera. We thank Altera and Xilinx for their donation of tools and hardware. Please see the CoRAM project page for complete and up-to-date details.
- Cagla Cakir (Advised by Prof. Ken Mai)
- Yu Wang
- Demo and Downloads
- ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects. Eric Chung and Michael Papamichael. Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2013.
- C-To-CoRAM: Compiling Perfect Loop Nests to the Portable CoRAM Abstraction. Gabriel Weisz and James C. Hoe. Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2013. (pdf)
- Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes. Berkin Akın, Peter A. Milder, Franz Franchetti and James C. Hoe. Proc. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2012. (pdf)
- CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs. Michael Papamichael and James C. Hoe. Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012. (pdf)
- Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-Based Computing. Eric S. Chung, Michael K. Papamichael, Gabriel Weisz, James C. Hoe, and Ken Mai. Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012. (pdf)
- CoRAM: An In-Fabric Memory Architecture for FPGA-Based Computing. Eric S. Chung. PhD Thesis, August 2011. (pdf)
- CoRAM: An In-Fabric Memory Architecture for FPGA-based Computing. Eric S. Chung, James C. Hoe, and Kenneth Mai. Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pp 97~106, February 2011. (pdf)
- Single-chip Heterogeneous Computing: Does the future include Custom Logic, FPGAs, and GPUs? Eric S. Chung, Peter A. Milder, James C. Hoe, and Kenneth Mai. Proc. ACM/IEEE International Symposium on Microarchitecture (MICRO), pp 53~64, December 2010. (pdf)
- Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2012) (co-organized with Derek Chiou and Joel Emer)