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18-643_course_schedule_fall_2017 [2017/10/27 12:47] – [References] edit | 18-643_course_schedule_fall_2017 [2017/11/15 16:24] – [Schedule and Lecture Notes] edit |
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| 11 | 11/7 | L18 | Coarse-Grained Reconfigurable Array\\ and Overlay Architecture | Review [Zain-ul-Abdin09] or [Severance12] | | | | 11 | 11/7 | L18 | Coarse-Grained Reconfigurable Array\\ and Overlay Architecture | Review [Zain-ul-Abdin09] or [Severance12] | | |
| | 11/9 | L19 | FPGAs in Datacenter\\ **Guest Lecture: Michael Papamichael (MSR)** | Review [Putnam14] or [Caulfield16] | | | | | 11/9 | L19 | FPGAs in Datacenter\\ **Guest Lecture: Michael Papamichael (MSR)** | Review [Putnam14] or [Caulfield16] | | |
| 12 | 11/14 | L20 | Applications: streaming and graphics | Review [Prabhakar17] or [Hegarty16] | | | | 12 | 11/14 | L20 | DSL: streaming and graphics | Review [Prabhakar17] or [Hegarty16] | | |
| | 11/16 | L21 | FPGA in Algorithmic Trading\\ **Guest Lecturer: Todd Strader (Two Sigma)** | Review [Li16] or [Wang17] | | | | | 11/16 | L21 | FPGA in Algorithmic Trading\\ **Guest Lecturer: Todd Strader (Two Sigma)** | Review [Li16] or [Wang17] | | |
| 13 | 11/21 | L22| Applications: irregular parallelism | Review [Ham16] or [Li17] | | | | 13 | 11/21 | L22| Irregular Parallelism | Review [Ham16] or [Li17] | | |
| | 11/23 | ^ Thanksgiving | | | | | | 11/23 | ^ Thanksgiving | | | |
| 14 | 11/28 | L23 | Slack | | | | | 14 | 11/28 | L23 ^ no class meeting | | | |
| | 11/30 | L24 | Applications: machine learning | Review [Han17] or [Jouppi17] with week 13 | | | | | 11/30 | L24 | Machine Learning | Review [Han17] or [Jouppi17] with week 13 | | |
| 15 | 12/5 | ^ Term Project Student Presentations | | | | | 15 | 12/5 | ^ Term Project Student Presentations | | | |
| | 12/7 | ^ Term Project Student Presentations | | | | | | 12/7 | ^ Term Project Student Presentations | | | |
* [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086414 |[Tessier15]]] R. Tessier, et al., "Reconfigurable Computing Architectures," Proceedings of the IEEE, March 2015. | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086414 |[Tessier15]]] R. Tessier, et al., "Reconfigurable Computing Architectures," Proceedings of the IEEE, March 2015. |
* [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015. | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015. |
* [[https://dl.acm.org/citation.cfm?id=3050220.3050234 |[[Wang17]]] H. Wang, et al., "P4FPGA: A Rapid Prototyping Framework for P4," Proceedings of SOSR, 2017. | * [[https://dl.acm.org/citation.cfm?id=3050220.3050234 |[Wang17]]] H. Wang, et al., "P4FPGA: A Rapid Prototyping Framework for P4," Proceedings of SOSR, 2017. |
* [[http://ieeexplore.ieee.org/document/7294017/ |[Weisz15]]] G. Weisz, et al., "CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing," Proceedings of FPL, 2015. | * [[http://ieeexplore.ieee.org/document/7294017/ |[Weisz15]]] G. Weisz, et al., "CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing," Proceedings of FPL, 2015. |
* [[http://ac.els-cdn.com/S0141933108001038/1-s2.0-S0141933108001038-main.pdf?_tid=bbf45bee-954a-11e7-bf1b-00000aacb362&acdnat=1504953567_b2447610e91a6e26c21bc141e06ad029 |[Zain-ul-Abdin09]]] Zain-ul-Abdin, et al., "Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing," Microprocessors and Microsystems, Volume 33, Issue 3, May 2009. | * [[http://ac.els-cdn.com/S0141933108001038/1-s2.0-S0141933108001038-main.pdf?_tid=bbf45bee-954a-11e7-bf1b-00000aacb362&acdnat=1504953567_b2447610e91a6e26c21bc141e06ad029 |[Zain-ul-Abdin09]]] Zain-ul-Abdin, et al., "Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing," Microprocessors and Microsystems, Volume 33, Issue 3, May 2009. |
* [[http://dl.acm.org/citation.cfm?id=2689060 |[Zhang15]]] C. Zhang, et al., "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of ISFPGA, 2015. | * [[http://dl.acm.org/citation.cfm?id=2689060 |[Zhang15]]] C. Zhang, et al., "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of ISFPGA, 2015. |
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