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18-447 Course Schedule, Spring 2020

Reading assignments are to be completed BEFORE coming to class. (P&H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it helpful to preview lecture notes from Spring 2019 before class. There will be additional assigned readings from research papers.

  • Part 1: L1~L12 Microrocessors
  • Part 2: L13~L19 Memory and I/O
  • Part 3: L20~L27 Parallel

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Week Date L# Topic Readings Lab Week
1 1/13 L1 Introduction P&H Ch1 No lab meeting
this week
1/15 L2 RISC-V RV32I ISA P&H Ch2
2 1/20 No classes (Martin Luther King, Jr. Day) Lab 1A/B start
1/22 L3 Single-Cycle Implementation P&H 4.1~4.4
3 1/27 L4 ISA Design P&H Ch2 Lab 1A due
1/29 L5 Performance P&H Ch1.6~1.9
4 2/3 L6 Multi-Cycle Implementations P&H Appendix C Lab 1B due
2/5 L7 Pipelining: Basics P&H Ch4.5~4.6
5 2/10 L8 Pipelining: Data Hazard and Resolution P&H Ch4.7 Lab 2 start
2/12 L9 Pipelining: Control Hazard and Resolution P&H Ch4.8
6 2/17 L10 Pipelining: Branch Prediction P&H Ch4.8 mid-Lab 2 check-off
2/19 L11 Pipelining: Exceptions P&H Ch4.9 and rest
7 2/24 Midterm 1 in Class Lab 2 due
2/26 L12 Power and Energy
8 3/2 L13 Busses and I/O P&H Ch5.5 Lab 3 start
3/4 L14 Memory Technology and Organization P&H Ch5.1, 5.2
3/9 No classes (Spring Break)
3/11 No classes (Spring Break)
9 3/16 L15 Caches P&H Ch5.3
3/18 L16 More caches P&H Ch5.4, 5.9
10 3/23 L17 VM: protection and paging P&H Ch5.6~5.8 Lab 3 due
3/25 L18 VM: page tables and TLB P&H Ch5.6~5.8
11 3/30 L19 VM: modern systems Rest of Ch5 and paper Lab 4 start
4/1 L20 ILP to multicore
12 4/6 Midterm 2 in class Lab 4 status check
4/8 L21 Parallel Computer Architecture P&H Ch6
13 4/13 L22 Multithreaded Programming
4/15 L23 Parallel Performance P&H Ch5.15
14 4/20 L24 Cache Coherence P&H Ch5.10
4/22 L25 Synchronization P&H Ch2.11, 5.14
15 4/27 L26 Interconnects Lab 4 due
4/29 L27 Hardware Acceleration
TBD Final Exam