IEEE Computer Society Workshop on VLSI
19-20 April, Orlando, Florida
FINAL PROGRAM
Thursday April 19, 2001
Welcome and Opening of the WVLSI'01 (8:00-8:10
am)
Vijaykrishnan Narayanan, General Chair
Asim Smailagic, Program Chair
-
Emerging Trends in VLSI Sytems (8:10 - 10:50 am)
-
Energy Locality and Trends in Low Power Electronic Design
Daniel P. Siewiorek
Carnegie Mellon University
-
Towards Very High Bandwidth Wireless Handheld Devices
John Glossner
Sandbridge Technologies, Inc.
-
Defect Tolerant Molecular Electronics
Philip Kuekes
Hewlett Packard
-
Energy-Efficient Link Layer for Wireless Microsensor Networks
Eugene Shih, Benton Calhoun, Seong Cho, Anantha Chandrakasan
MIT
-
Electronic Nanotechnology and Reconfigurable Computing
Seth Goldstein
Carnegie Mellon University
Coffee Break (10:50 - 11:05 am)
-
System Level Design Examples I (11:05 am - 12:35 pm)
-
A Multi-PLL Clock Distribution Architecture for Gigascale Integration
Martin-Sain-Laurent, Intel, and Madhavan Swaminathan, Georgia Institute
of
Technology
-
Structural Design Composition for C++ Hardware Models
F. Doucet, V. Sinha, R. Gupta
University of California at Irvine
-
Design and Implementation of a Coarse-Grained Dynamically Reconfigurable
Hardware Architecture
Jurgen Becker, Thilo Pionteck, Christian Habermann, Manfred Glesner
Darmstadt University of Technology, Germany
Lunch (12:35 - 1:30 pm)
-
Advanced VLSI Design (1:30 - 3:30 pm)
-
Application of Output Prediction Logic to Differential CMOS
Su Kio, Larry McMurchie, Carl Sechen
University of Washington, Seattle
-
Current-Sensing Techniques for Global Interconnect in VDSM CMOS
Atul Maheshwari, Wayne Burleson
University of Massachusetts
-
Reducing Register and Phase Requirements for Synchronous Circuits Derived
Using Software Pipelining Techniques
N. Chabini, El M. Aboulhamid, Y. Savaria
Universite de Montreal, Canada
-
Built-In Self-Testable Data Path Synthesis
Laurence Tianruo Yang (1,2) and Jon Muzio (2)
(1) St. Francis Xavier University, Canada, (2) University of Victoria, Canada
Coffee Break (3:30-3:45 pm)
-
Advanced Circuit Design (3:45 - 5:45 pm)
-
Load-Sensitive Flip-Flop Characterization
Seongmoo Heo, Krste Asanovic
MIT
-
A Linear Threshold Gate Implementation in Single Electron Technology
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
Delft University of Technology, Netherlands
-
Evaluating Metastability in Electronic Circuits for Random Number Generation
Shonda Walker and Simon Foo
Florida A&M University and Florida State University
-
Improved Power Estimation For Behavioral and Gate Level Designs
Ronnie Wright
DCS Corporation, U.S. Army TACOM
Panel: Nanoelectronics and Molecular Computing (6:00 - 7:00
pm)
Banquet Dinner (7:00 - 8:30 pm)
Friday April 20, 2001
-
System Level Design Examples II (8:15 - 9:15 am)
-
System Design of Low-Energy Wearable Computers with Wireless Networking
Asim Smailagic, Daniel P. Siewiorek
Carnegie Mellon University
-
A Heterogeneous Multiprocessor Architecture for Low-Power Audio Signal
Processing Applications
Ozgun Paker, Jens Sparso, Niels Haandbaek, Mogens Isager, and Lars Skovby Nielsen
Technical University of Denmark, Denmark
Coffee Break (9:15 - 9:30 am)
-
Low Power Design (9:30 - 11:30 am)
-
VLIW Scheduling for Energy and Performance
A. Parikh, M. Kandemir, N. Vijaykrishnan, M.J. Irwin
The Pennsylvania State University
-
A Low-Energy Adaptive Bus Coding Scheme
Benjamin Bishop
University of Georgia
-
LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth
Hao Li, Wai-Kei Mak, Srinivas Katkoori
University of South Florida
-
A Low Power SIMD Architecture for Affine-Based Texture Mapping
Wael Badawy
University of Calgary
Lunch (11:45 am - 12:45 pm)
-
Advances in Analog-to-Digital Converters Design (12:45- 1:45 pm)
-
A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip
Applications
Jincheol Yoo, Kyusun Choi, Ali Tangel
The Pennsylvania State University
-
Transient Fault Sensitivity Analysis of Analog-to-Digital Convereters (ADCs)
M. Singh, R. Rachala and I. Koren
University of Massachusetts
-
Low-Power Design of ALUs (1:45 - 2:45 pm)
-
A Novel Architecture for Low-Power Design of Parallel Multipliers
Ayman Fayed, Magdy Bayoumi
University of Louisiana
-
A Pipelined Logarithmic Number System ALU
Mark Arnold
University of Manchester, England / University of Wyoming
Coffee Break (2:45 - 3:00 pm)
-
Issues in System Design (3:00 - 4:00 pm)
-
A Hybrid Wave-Pipelined Network Router
J. G. Delgado-Frias, J. Nyathi
State University of New York
-
A Memory Management Approach for Efficient Implementation of Multimedia
Kernels on Programmable Architectures
M. Dasigenis, N.Kroupis, A.Argyriou, K.Tatas, D. Soudris, N.Zervas
Democritus University and University of Patras, Grece
PANEL: Quantum Computing (4:15 - 5:15 pm)
Concluding Remarks (5:15 - 6:00 pm)
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