18-548 /15-548
Memory System Architecture

Course Announcement

August 20, 1998
Course Instructor: Prof. Phil Koopman

Note: THE COURSE MEETING TIMES HAVE BEEN CHANGED!

Lecture: Monday & Wednesday 9:00-10:20 AM in DH 2122
Recitation: Friday 10:30-11:20 AM in HH B131

As increased CPU speed and complexity yield higher peak performance ratings, it becomes ever more difficult for the rest of the computer system to keep up. To deliver high sustained performance on real applications, the entire system must be balanced in both bandwidth and latency. This course is about analyzing and designing high performance computer systems to support modern CPUs. In other words, students will learn how to convert the potential of a modern CPU into a computer system that can actually deliver high performance.

The course will be based on the non-CPU portions of Cragon's book Memory Systems and Pipelined Processors:
Chapter 1: Memory Systems
Chapter 2: Caches
Chapter 3: Virtual Memory
Chapter 4: Memory Addressing and I/O Coherency
Chapter 5: Interleaved Memory and Disk Systems
Chapter 11: Vector Processors

An on-line draft topic coverage diagram is available. Additional reading material will be made available as necessary, but Cragon will be the only required textbook that must be purchased. The course coverage is largely the same as 18-742 as it was offered in Spring 1998, minus a term project but plus some traditional homework assignments and with most of the 18-742 homework assignments converted into somewhat more structured lab experiences.

Supplemental reading will be recommended from Hennessey & Patterson, Computer Architecture: A Quantitative Approach (2nd edition) and other sources either on the World Wide Web or placed on reserve in the library as appropriate.

These days much of system design involves combining existing components, or even just trying to get good performance from a complete off-the-shelf system. While many current course offerings focus on design and synthesis, this course will instead emphasize experimentation and analysis as aids to understanding and exploiting system architectures. The main course tools will be the Dinero cache simulator and the Atom instrumentation package for the Alpha architecture (both of these are for performance analysis, not synthesis tools for creating computer designs).

In addition to in general learning about how computers work beyond the CPU, students in this course will specifically learn:

• How the various levels of memory hierarchy work (with focus on detailed understanding of operation, and why things work as they do, rather than memorization of terminology)
• Specific tradeoffs among different memory hierarchy mechanisms and policies in terms of latency, bandwidth, balance and cost
• Use of the Dinero cache simulator and Atom instrumentation tool for quantifying design tradeoffs and finding performance problems
• How to probe hardware using ordinary C code and thereby determine the memory hierarchy design parameters
• Techniques for significantly speeding up software by exploiting memory hierarchy characteristics, by up to a factor of 2000%
• How traditional mainframe and supercomputer architectural ideas are being applied to current and future microprocessors to improve performance.

This is a 12-unit 500-level course, meaning that a typical Senior is expected to spend 12 hours per week on it, including classroom time. Course term projects currently required in 18-742 will not be required in 18-548. The course workload will include:

• Two 80-minute lectures per week
• One 50-minute recitation section per week
• Approximately weekly homework assignments
• "Lab" assignments, largely the same as the current homework assignments in 18-742 (the size vs. frequency of the lab assignments is still under consideration). These assignments can be performed via telnet to the course computers and do not require physical presence in a lab room. They will give a realistic experience of real-world computer architecture tasks, and thus require significant simulation and performance experimentation runs as well as analysis and graphing of experimental data sets.
• Three in-class exams

Students in 18-548 are required to bring a solid computer engineering background to the course, including prerequisites of 18-545 Advanced Digital Design Project, or preferably 18-547 Superscalar Processor Design. Students are assumed to have a general knowledge of the operation of superscalar CPUs when entering the course. Students are strongly cautioned that taking these prerequisites concurrently with rather than before 18-548 is a bad idea, unless they have already taken a strong architecture course at another university.

Prerequisites for 15-548 are 18-347/15-347 Introduction to Computer Architecture and 15-412 Operating Systems. Additionally, students with graduate standing can sign up without prerequisites, as can seniors with instructor permission. 18-548 and 15-548 are cross-listings, meaning that they are the same course with the same meeting times and same assignments. If CS students feel they are missing information to understand the course material, they should contact the course staff immediately to resolve the problem. Since this is the first time this material is being offered as a CS course, an appropriate level of supplemental lectures or coverage in recitation sessions will be provided to plug any "holes".

It is planned that this course will satisfy "coverage" requirements. It is not a capstone design course. It does not satisify "depth" requirements because the prerequisites of 18-545 or 18-547 already satisfy those requirements. The specifics this course description are subject to change to meet the needs of students and the ECE Department.

koopman@cmu.edu